A Parallel Parsing VLSI Architecture for Arbitrary Context Free Grammars

In this paper we propose a fixed size one-dimensional VLSI architecture for the parallel parsing of arbitrary context free (CF) grammars, based on Earley’s algorithm. The algorithm is transformed into an equivalent double nested loop with loopcarried dependencies. We first map the algorithm into a 1-D array with unbounded number of cells. The time complexity of this architecture is O(n), which is optimal. We next propose the partitioning into fixed number of off-the-shelf processing elements. Two alternative partitioning strategies are presented, considering restrictions, not only in the number of the cells, but also in the inner structure of each cell. In the most restricted case, the proposed architecture has time complexity O(n/p*k), where p is the number of available cells and the elements inside each cell are at most k. Index Terms --Parallel parsing, Earley’s algorithm, partitioning, systolic array, mapping.